This invention relates to a phase lock loop circuit for carrying out phase lock operation in high speed. Such a phase lock loop circuit is particularly useful for use in channel designation for a digital radio communication device.
Recently, it is has become necessary to provide a digital mobile radio telephone set which utilizes a time divisional multiple access system. In such a digital mobile radio telephone set, it is necessary to change one talk channel to another talk channel in high speed. In this event, the digital mobile radio telephone set requires a phase lock loop circuit which can carry out a phase lock operation in high speed.
As well known in the art, the phase lock loop circuit comprises a reference signal generator, a voltage controlled oscillator, a frequency divider, and a phase comparator. The reference signal generator generates a reference signal having a reference frequency and a reference phase. The voltage controlled oscillator is supplied with an oscillator input signal and produces a phase controlled signal having an output frequency in response to the oscillator input signal. The frequency divider has a predetermined frequency division ratio N where N represents a positive integer. The phase controlled signal is divided into a frequency divided signal by the frequency divider. The frequency divided signal has a signal phase and a divided frequency which depends upon the predetermined frequency division ratio N. The phase comparator is supplied with the reference signal and the frequency divided signal and compares the signal phase with the reference phase to produce a comparison result signal representative of a phase error between the reference phase and the signal phase.
The phase lock loop circuit further comprises a filter control circuit and a loop filter connected to the filter control circuit. As will later be described in more detail, the filter control circuit is connected to the phase comparator and serves for supplying a filter control signal to the loop filter in response to the comparison result signal. The loop filter comprises a filter capacitor which is selectively charged and discharged in response to the filter control signal. The loop filter thereby filters the filter control signal into a filtered signal to supply the voltage controlled oscillator with the filtered signal as the oscillator input signal. Thus, a phase control loop is established so that the phase controlled signal has an output frequency N times as large as the reference frequency.
In such a phase lock loop circuit, it is proposed to increase a cut-off frequency of the loop filter in order to carry out the phase lock operation at high speeds. The phase control loop has, however, a degraded stability in a stationary state when the cut-off frequency is increased.
In order to avoid the above-described disadvantage, it is proposed that the phase lock loop circuit comprise a frequency control circuit for varying the cut-off frequency of the loop filter. As will later be described in more detail, the frequency control circuit controls the loop filter so that the loop filter has a high cut-off frequency in the phase lock operation and that the loop filter has a low cut-off frequency in the stationary state. In this event, the cut-off frequency varies discontinuously between the high cut-off frequency and the low cut-off frequency. This means that a voltage of the filtered signal varies discontinuously. As a result, the output frequency of the phase controlled signal changes to an unexpected value.